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r01ds0029ej0001 rev.0.01 page 1 of 75 sep 30, 2010 preliminary datasheet pd70f3826, 70f3827 , 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3 835, 70f3836, 70f3837 ? v850es/je3-e, v850es/ jf3-e, v850es/jg3-e ? renesas mcu description the pd70f3826, 70f3827, 70f3828, 70f3829 (v850es/jf3-e), and pd70f3830, 70f3831, 70f3832, 70f3833 (v850es/jf3-e), and pd70f3834, 70f3835, 70f3836, 70f3837 (v850es/jg3-e) are pr oducts of the v850 32-bit single-chip microcontrollers, and include peripheral functions such as rom/ram, timer/count ers, serial interfaces, an a/d converter, a dma controller , a can controller , a usb function controller , and a ethernet controller. in addition to their high real-time responsiveness and one-clo ck-pitch execution of instru ctions, the v850es/je3-e, v850es/jf3-e, and v850es/jg3-e include inst ructions executed via a hardware mult iplier, saturation instructions, and bit manipulation instructions. detailed function descriptions are prov ided in the following u ser?s manuals. be sure to read them before designing. v850es/je3-e, v850es/jf3-e, v850es/jg3-e ha rdware user?s manua l: to be prepared v850es architecture user?s manual: u15943e features { number of instructions: 83 { minimum instruction execution time: 20 ns (@ 50 mhz operation with main clock (f xx )) { clock ? main clock oscillation: f x = 3 to 6.25 mhz ? subclock oscillation: f xt = 32.768 khz ? internal oscillation: f r = 220 khz (typ.) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { memory space: 64 mb linear address space { internal memory flash memory: 64/128/256 kb ram: 32/48/64 kb (including 16 kb of data ram area) { i/o lines total: 26/42/62 { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 63/78/85 sources { timer/counters 16-bit timer/event counter aa (taa): 5 channels 16-bit timer/event counter ab (tab): 1 channel motor control function supported 16-bit interval timer m (tmm): 4 channels 16-bit encoder timer t (tmt): 1 channel { real-time counter: 1 channel { watchdog timer: 1 channel { real-time output function: 6 channels { a/d converter: 10-bit resolution 10/10 channels { ethernet controller: 1 channel { usb function controller: 1 channel { serial interface ? can :1 channel ( pd70f3829, 70f3833, 70f3837 only) ? asynchronous serial interface c(uartc): 3/4 channels ? clocked serial interface f(csif): 2/3/5 channels ? i 2 c bus interface: 2/3 channels { dma controller: 4 channels { power save function: halt/idle1/idle2/stop/subclock/sub-idle mode { on-chip debug function { package: 64-pin lqfp (v850es/je3-e) 64-pin wqfn (v850es/je3-e) 80-pin lqfp (v850es/jf3-e) 100-pin lqfp (v850es/jg3-e) 113-pin fbga (under planing) { operating supply voltage: 2.85 to 3.6 v r01ds0029ej0001 rev.0.01 sep 30, 2010
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 2 of 75 sep 30, 2010 function list (v850es/je3-e) generic name v850es/je3-e product name pd70f3826 pd70f3827 pd70f3828 pd70f3829 flash memory 64 kb 128 kb 256 kb 256 kb internal ram 16 kb 32 kb 48 kb 48 kb internal memory data ram 16 kb 16 kb 16 kb 16 kb memory space 64 mb general-purpose register 32 bits 32 registers main clock oscillation pll mode : f x = 3 to 6.25 mhz, f xx = 24 to 50 mhz (multiplication by 8) clock through mode : f x = 3 to 6.25 mhz ( internal : f xx = 3 to 6.25 mhz) subclock oscillation f xt = 32.768 khz internal oscillation f r = 220 khz (typ.) clocks minimum instruction execution time 20 ns (@ 50 mhz operation wi th main system clock (f xx )) i/o ports i/o: 26 (5 v tolerant : 12) 16-bit taa 5 channels (among which two cha nnels have the interval function only) 16-bit tab ? 16-bit tmm 4 channels 16-bit tmt 1 channel (i nterval function only) motor control ? watch timer 1 channel (rtc) timer wdt 1 channel real-time output function 6 bits 1 channel 10-bit a/d converter 10 channels csif/uartc 1 channel csif/uartc/i 2 c 1 channel csif ? uartc/i 2 c 1 channel ? serial interface uartc/i 2 c/can ? 1 channel usb function 1 channel ethernet controller 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram) external note 1, 2 7(7) 7(7) 7(7) 7(7) interrupt source internal 54 54 54 58 power-save function halt/idle1/idle 2/stop/subclock/sub-idle modes reset factor reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube ? , minicube2 supported operating supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 64-pin plastic lq fp (fine pitch) (10 10 mm), 64-pin plastic wqfn (9 9 mm), notes 1. the figure in parentheses indicates the number of external interrupts that can release the stop mode. notes 2 . include nmi.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 3 of 75 sep 30, 2010 function list (v850es/jf3-e) generic name v850es/jf3-e product name pd70f3830 pd70f3831 pd70f3832 pd70f3833 flash memory 64 kb 128 kb 256 kb 256 kb internal ram 16 kb 32 kb 48 kb 48 kb internal memory data ram 16 kb 16 kb 16 kb 16 kb memory space 64 mb general-purpose register 32 bits 32 registers main clock oscillation pll mode : f x = 3 to 6.25 mhz, f xx = 24 to 50 mhz (multiplication by 8) clock through mode : f x = 3 to 6.25 mhz ( internal : f xx = 3 to 6.25 mhz) subclock oscillation f xt = 32.768 khz internal oscillation f r = 220 khz (typ.) clocks minimum instruction execution time 20 ns (@ 50 mhz operation wi th main system clock (f xx )) i/o ports i/o: 42 (5 v tolerant : 28) 16-bit taa 5 channels 16-bit tab 1 channel 16-bit tmm 4 channels 16-bit tmt 1 channel motor control 1 channel watch timer 1 channel (rtc) timer wdt 1 channel real-time output function 6 bits 1 channel 10-bit a/d converter 10 channels csif/uartc 1 channel csif/uartc/i 2 c 2 channels csif ? uartc/i 2 c 1 channel ? serial interface uartc/i 2 c/can ? 1 channel usb function 1 channel ethernet controller 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram) external note 1, 2 19(19) 19(19) 19(19) 19(19) interrupt source internal 57 57 57 61 power-save function halt/idle1/idle 2/stop/subclock/sub-idle modes reset factor reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube, minicube2 supported operating supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 80-pin plastic lq fp (fine pitch) (12 12 mm) notes 1. the figure in parentheses indicates the number of external interrupts that can release the stop mode. notes 2 . include nmi.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 4 of 75 sep 30, 2010 function list (v850es/jg3-e) generic name v850es/jg3-e product name pd70f3834 pd70f3835 pd70f3836 pd70f3837 flash memory 64 kb 128 kb 256 kb 256 kb internal ram 16 kb 32 kb 48 kb 48 kb internal memory data ram 16 kb 16 kb 16 kb 16 kb memory space 64 mb general-purpose register 32 bits 32 registers main clock oscillation pll mode : f x = 3 to 6.25 mhz, f xx = 24 to 50 mhz (multiplication by 8) clock through mode : f x = 3 to 6.25 mhz ( internal : f xx = 3 to 6.25 mhz) subclock oscillation f xt = 32.768 khz internal oscillation f r = 220 khz (typ.) clocks minimum instruction execution time 20 ns (@ 50 mhz operation wi th main system clock (f xx )) i/o ports i/o: 62 (5 v tolerant : 35) 16-bit taa 5 channels 16-bit tab 1 channel 16-bit tmm 4 channels 16-bit tmt 1 channel motor control 1 channel watch timer 1 channel (rtc) timer wdt 1 channel real-time output function 6 bits 1 channel 10-bit a/d converter 10 channels csif/uartc 1 channel csif/uartc/i 2 c 2 channels csif 2 channels uartc/i 2 c 1 channel ? serial interface uartc/i 2 c/can ? 1 channel usb function 1 channel ethernet controller 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram) external note 1, 2 22(22) 22(22) 22(22) 22(22) interrupt source internal 61 61 61 65 power-save function halt/idle1/idle 2/stop/subclock/sub-idle modes reset factor reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube, minicube2 supported operating supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 100-pin plastic lq fp (fine pitch) (14 14 mm), 113-pin plastic fbga note3 notes 1. the figure in parentheses indicates the number of external interrupts that can release the stop mode. notes 2 . include nmi. 3. under planning.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 5 of 75 sep 30, 2010 applications { applications that requi re ethernet controller home audio, printers, and scanners. ordering information ? v850es/je3-e part number package on-chip flash memory pd70f3826gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) 64 kb pd70f3827gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) 128 kb pd70f3828gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) 256 kb pd70f3829gb-gah-ax 64-pin plastic lqfp (fine pitch) (10 10) 256 kb pd70f3826k8-6b4-ax 64-pin plastic wqfn (9 9) 64 kb pd70f3827k8-6b4-ax 64-pin plastic wqfn (9 9) 128 kb pd70f3828k8-6b4-ax 64-pin plastic wqfn (9 9) 256 kb pd70f3829k8-6b4-ax 64-pin plastic wqfn (9 9) 256 kb ? v850es/jf3-e part number package on-chip flash memory pd70f3830gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) 64 kb pd70f3831gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) 128 kb pd70f3832gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) 256 kb pd70f3833gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) 256 kb ? v850es/jg3-e part number package on-chip flash memory pd70f3834gc-ueu-ax 100-pin plasti c lqfp (fine pitch) (14 14) 64 kb pd70f3835gc-ueu-ax 100-pin plasti c lqfp (fine pitch) (14 14) 128 kb pd70f3836gc-ueu-ax 100-pin plasti c lqfp (fine pitch) (14 14) 256 kb pd70f3837gc-ueu-ax 100-pin plasti c lqfp (fine pitch) (14 14) 256 kb pd70f3837f1-cah-ax note 113-pin plastic fbga (8 8) 256 kb note under planning remark the v850es/jx3-e microcontrollers are lead-free products.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 6 of 75 sep 30, 2010 pin configuration ? v850es/je3-e 64-pin plastic lqfp (fine pitch) (10 10) pd70f3826gb-gah-ax pd70f3827gb-gah-ax pd70f3828gb-gah-ax pd70f3829gb-gah-ax av ref0 av ss p02/nmi p20/intp01 v dd regc note2 v ss x1 x2 reset xt1 xt2 p30/txdc0/sif2/tiaa00/toa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p50/intp07/ddi p1mdio p1mdc p1col p1crs ev dd v ss flmd0 note1 regc note2 v dd p1rxclk p1rxer p1rxdv p1rxd3 p1rxd2 p1rxd1 p1rxd0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst udmf udpf uv dd ev dd v ss p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p42/sckf0/tiaa40/toaa40/rtp02 p41/sof0/rxdc3/scl01/rtp01 p40/sif0/txdc3/sda01/rtp00 p37/rxdc2/scl02(/crxd0 note3 ) p36/txdc2/sda02(/ctxd0 note3 ) pdl5/flmd1 notes 1. connect to v ss in normal mode. 2. connect the regc pin to v ss via a 4.7 f (preliminary value) capacitor. 3. pd70f3829 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 7 of 75 sep 30, 2010 ? v850es/je3-e 64-pin plastic wqfn (9 9) pd70f3826k8-6b4-ax pd70f3827k8-6b4-ax pd70f3828 k8-6b4-ax pd70f3829k8-6b4-ax exposed die pad av ref0 av ss p02/nmi p20/intp01 v dd regc note2 v ss x1 x2 reset xt1 xt2 p30/txdc0/sif2/tiaa00/toa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p50/intp07/ddi p1mdio p1mdc p1col p1crs ev dd v ss flmd0 note1 regc note2 v dd p1rxclk p1rxer p1rxdv p1rxd3 p1rxd2 p1rxd1 p1rxd0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst udmf udpf uv dd ev dd v ss p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p42/sckf0/tiaa40/toaa40/rtp02 p41/sof0/rxdc3/scl01/rtp01 p40/sif0/txdc3/sda01/rtp00 p37/rxdc2/scl02(/crxd0 note3 ) p36/txdc2/sda02(/ctxd0 note3 ) pdl5/flmd1 notes 1. connect to v ss in normal mode. 2. connect the regc pin to v ss via a 4.7 f (preliminary value) capacitor. 3. pd70f3829 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 8 of 75 sep 30, 2010 ? v850es/jf3-e 80-pin plastic lqfp (fine pitch) (12 12) pd70f3830gk-gak-ax pd70f3831gk-gak-ax pd70f3832gk-gak-ax pd70f3833gk-gak-ax 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ref0 av ss p02/nmi p20/intp01 v dd regc note2 v ss x1 x2 reset xt1 xt2 p23/sif1/txdc1/sda00/intp03 p24/sof1/rxdc1/scl00/intp04 p25/sckf1/tiaa30/toaa30 p26/tiaa31/toa31/intp05 p30/txdc/sif2/tiaa00/toaa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p50/intp07/ddi p91/toab1b1/tiab10/kr/toab10 p90/toab1t1/toab11/tiab11/kr0/intp12 p1mdio p1mdc p1col p1crs ev dd ev ss flmd0 note1 v dd p1rxclk p1rxer p1rxdv p1rxd3 p1rxd2 p1rxd1 p1rxd0 p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst p913/intp19 udmf udpf uv dd ev dd v ss p96/tecr0/tit00/kr6/tot00 p97/tenc00/tit01/kr7/tot01 p98/tec01/intp17 p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p42/sckf0/tiaa40/toaa40/rtp02 p41/sof0/rxdc3/scl01/rtp01 p78/ani8 p79/ani9 p40/sif0/txdc3/sda01/rtp00 p37/rxdc2/scl02(/crxd0 note3 ) p36/txdc2/sda02(/ctxd0 note3 ) p35/tiaa21/toaa21/toaa1off/intp06 pdl5/flmd1 p912/toab1off/intp18 p95/toab1b3/evtab1/kr5/intp16 p94/toab1t3/tiab13/kr4/intp15 p93/toab1b2/trgab1/kr3/intp14 p92/toab1t2/toab12/tiab12/kr2/intp13 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 regc note2 notes 1. connect to v ss in normal mode. 2. connect the regc pin to v ss via a 4.7 f (preliminary value) capacitor. 3. pd70f3833 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 9 of 75 sep 30, 2010 ? v850es/jg3-e 100-pin plastic lqfp (fine pitch) (14 14) pd70f3834gc-ueu-ax pd70f3835gc-ueu-ax pd70f3836gc-ueu-ax pd70f3837gc-ueu-ax 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p45/tiaa41/toaa41/rtp05 p44/rtp04 p43/rtp03 p42/sckf0/tiaa40/toaa40/rtp02 p41/sof0/rxdc3/scl01/rtp01 p40/sif0/txdc3/sda01/rtp00 pdl7 pdl6 p37/rxdc2/scl2(/crxd0 note3 ) p36/txdc2/sda2(/ctxd0 note3 ) p35/sckf4/tiaa21/toaa21/toaa1off/intp06 pdl5/flmd1 p912/toab1off/intp18 p95/toab1b3/evtab1/kr5/intp16 p94/toab1t3/toab13/tiab13/kr4/intp15 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst p913/sif3/intp19 p914/sof3/intp20 p915/sckf3 pdl8 pdl9 udmf udpf uv dd ev dd v ss p96/tecr0/tit00/kr6/tot00 p97/tenc00/tit01/kr7/tot01 p98/tenc01/intp17 pdl10 p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p93/toab1b2/trgab1/kr3/intp14 p92/toab1t2/toab12/tiab12/kr2/intp13 p91/toab1b1/tiab10/kr1/toab10 p90/toab1t1/toab11/tiab11/kr0/intp12 p1mdio p1mdc p1col p1crs pdl4 pdl3 ev dd v ss flmd0 note1 regc note2 v dd pdl2 pdl1 pdl0 p1rxclk p1rxer p1rxdv p1rxd3 p1rxd2 p1rxd1 p1rxd0 av ref0 av ss p02/nmi p03/intp00/adtrg/exclk p20/intp01 p21/rtcdiv/rtccl p22/rtc1hz/intp02 v dd regc note2 v ss x1 x2 reset xt1 xt2 p23/sif1/txdc1/sda00/int03 p24/sof1/rxdc1/scl00/intp04 p25/sckf1/tia30/toaa30 p26/tiaa31/toaa31/intp05 p30/txdc0/sif2/tiaa00/toa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p33/sif4/tia11/toaa11 p34/sof4/tiaa20/toaa20 p50/intp07/ddi notes 1. connect to v ss in normal mode. 2. connect the regc pin to v ss via a 4.7 f (preliminary value) capacitor. 3. pd70f3837 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 10 of 75 sep 30, 2010 pin identification adtrg: ani0 to ani9: asckc0: av ref0 : av ss : crxd0: ctxd0: dck: ddi: ddo: dms: drst: ev dd : evtab1: exclk flmd0, flmd1: intp00 to intp20: kr0 to kr7: nmi: p02, p03: p1col, p1crs, p1mdc, p1mdio, p1rxclk, p1rxd0 to p1rxd3, p1rxdv, p1rxer p1txclk, p1txd0 to p1txd3, p1txen, p1txer: p20 to p26 p30 to p37: p40 to p45: p50 to p54: p70 to p79: p90 to p98, p912 to p915: pdl0 to pdl10: regc: reset: rtc1hz, rtccl, rtcdiv: rtp00 to rtp05: a/d trigger input analog input asynchronous serial clock analog reference voltage grand for analog pin can receive data can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for external pin timer event count input usb clock flash programming mode external interrupt input key return non-maskable interrupt request port0 ethernet phy interface port2 port3 port4 port5 port7 port9 port dl regulator control reset real-time counter clock output real-time output port rxdc0 to rxdc3 sckf0 to sckf4: scl00 to scl02: sda00 to sda02: sif0 to sif4: sof0 to sof4: tecr0: tenc00, tenc01: tiaa00, tiaa01, tiaa10, tiaa11, tiaa20, tiaa21, tiaa30, tiaa31, tiaa40, tiaa41, tiab10 to tiab13, tit00, tit01: toaa00, toaa01, toaa10, toaa11, toaa20, toaa21, toaa30, toaa31, toaa40, toaa41, toab10 to toab13, toab1b1 to toab1b3, toab1t1 to toab1t3, tot00, tot01: toaa1off, toab1off trgab1: txdc0 to txdc3: udmf: udpf: uv dd : v dd : v ss : x1, x2: xt1, xt2: receive data serial clock serial clock serial data serial input serial output timer encoder clear input timer encoder input timer input timer output timer output off timer trigger input serial output usb data i/o (-) function usb data i/o (+) function power supply for external usb power supply ground crystal for main clock crystal for sub-clock
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 11 of 75 sep 30, 2010 internal block diagram ? v850es/je3-e 16-bit timer counter ab : 1 ch rtp00 to rtp05 rto wdt dcu rtc rom note2 note1 ram pc alu system registers 32-bit barrel shifter cpu timer / counter function serial interface function pdl5 p70 to p79 p50 to p54 p40 to p42 p30 to p32, p36, p37 p20 p02 av ref0 av ss ani0 to ani9 drst dms ddi dck ddo dma ethernet controller usb function intc intp01, intp07 to intp11 nmi clkout x1 x2 xt1 xt2 reset cg pll interrupt function debug function bcu tiaa00, tiaa10, tiaa40, tiaa01 toaa00, toaa10, toaa40, toaa01 16-bit interval timer m : 4 ch 16-bit timer counter t : 1 ch rxdc0, rxdc2, rxdc3 txdc0, txdc2, txdc3 asckc0 uartc : 3 ch csif : 2 ch sif0, sif2 sof0, sof2 sckf0, sckf2 iic0 : 2 ch sda01, sda02 scl01, scl02 can note 3 : 1 ch crxd0 ctxd0 16-bit timer/event counter aa : 5 ch a/d converter flmd0 flmd1 flash controller v dd regc ev dd uv dd v ss regulator multiplier 16 16 32 general-purpose registers 32 bits 32 ports notes 1. pd70f3826: 64 kb pd70f3827: 128 kb pd70f3828, 70f3829: 256 kb 2. pd70f3826: 32 kb (including 16 kb of data ram) pd70f3827: 48 kb (including 16 kb of data ram) pd70f3828, 70f3829: 64 kb (including 16 kb of data ram) 3. pd70f3829 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 12 of 75 sep 30, 2010 ? v850es/jf3-e 16-bit timer/event counter ab : 1 ch rtp00 to rtp05 kr0 to kr7 rto wdt key interrupt function dcu rtc rom note2 note1 ram pc alu system registers 32-bit barrel shifter cpu timer / counter function serial interface function pdl5 p90 to p98, p912, p913 p70 to p79 p50 to p54 p40 to p42 p30 to p32, p35 to p37 p20, p22 to p26 p02 av ref0 av ss ani0 to ani9 drst dms ddi dck ddo dma ethernet controller usb function intc intp01, intp03 to intp19 nmi clkout x1 x2 xt1 xt2 reset cg pll interrupt function debug function bcu tiaa00, tiaa10, tiaa30, tiaa40, tiaa01, tiaa21, tiaa31, toaa1off toab10 to toab13 toab1t1 to toab1t3, toab1b1 to toab1b3 tiab10 to tiab13, evtab1, trgab1, toab1off toaa00, toaa10, toaa30, toaa40, toaa01, toaa21, toaa31, 16-bit interval timer m : 4 ch tot00, tot01 tecr0, tenc00, tenc01, evtt0, tit00, tit01 16-bit timer/counter t : 1 ch rxdc0 to rxdc3 txdc0 to txdc3 asckc0 uartc : 4 ch csif : 3 ch sif0 to sif2 sof0 to sof2 sckf0 to sckf2 iic0 : 3 ch sda00 to sda02 scl00 to scl02 can note 3 : 1 ch crxd0 ctxd0 16-bit timer/event counter aa : 5 ch a/d converter flmd0 flmd1 flash controller v dd regc ev dd uv dd v ss regulator multiplier 16 16 32 general-purpose registers 32 bits 32 ports notes 1. pd70f3830: 64 kb pd70f3831: 128 kb pd70f3832, 70f3833: 256 kb 2. pd70f3830: 32 kb (including 16 kb of data ram) pd70f3831: 48 kb (including 16 kb of data ram) pd70f3832, 70f3833: 64 kb (including 16 kb of data ram) 3. pd70f3833 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 13 of 75 sep 30, 2010 ? v850es/jg3-e 16-bit timer/event counter ab : 1 ch rtp00 to rtp05 kr0 to kr7 rto wdt key interrupt function dcu rtc rom note2 note1 ram pc alu system registers 32-bit barrel shifter cpu timer / counter function serial interface function pdl0 to pdl15 p90 to p98, p912 to p915 p70 to p79 p50 to p54 p40 to p45 p30 to p37 p20 to p26 p02, p03 av ref0 av ss ani0 to ani9 drst dms ddi dck ddo dma ethernet controller usb function intc intp00 to intp20 nmi exclk clkout x1 x2 xt1 xt2 reset cg pll interrupt function debug function bcu tiaa00 to tiaa40, tiaa01 to tiaa41, toaa1off toab10 to toab13 toab1t1 to toab1t3, toab1b1 to toab1b3 tiab10 to tiab13, evtab1, trgab1, toab1off toaa00 to toaa40, toaa01 to toaa41 16-bit interval timer m : 4 ch tot00, tot01 tecr0, tenc00, tenc01, evtt0, tit00, tit01 16-bit timer/counter t : 1 ch rtc1hz rtccl rtcdiv rxdc0 to rxdc3 txdc0 to txdc3 asckc0 uartc : 4 ch csif : 5 ch sif0 to sif4 sof0 to sof4 sckf0 to sckf4 iic0 : 3 ch sda00 to sda02 scl00 to scl02 can note 3 : 1 ch crxd0 ctxd0 16-bit timer/event counter aa : 5 ch a/d converter flmd0 flmd1 flash controller v dd regc ev dd uv dd v ss regulator multiplier 16 16 32 general-purpose registers 32 bits 32 ports notes 1. pd70f3834: 64 kb pd70f3835: 128 kb pd70f3836, 70f3837: 256 kb 2. pd70f3834: 32 kb (including 16 kb of data ram) pd70f3835: 48 kb (including 16 kb of data ram) pd70f3836, 70f3837: 64 kb (including 16 kb of data ram) 3. pd70f3837 only.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 r01ds0029ej0001 rev.0.01 page 14 of 75 sep 30, 2010 contents 1. pin functions ................................................................................................. 15 1.1 port pins.................................................................................................... 15 1.2 non-port pins............................................................................................ 17 1.3 pin i/o circuits and recommended connection of unused pins............. 22 2. cpu functions ............................................................................................... 26 3. memory map .................................................................................................... 27 4. ports.................................................................................................................. 29 5. clock generation function ................................................................... 30 6. 16-bit timer/event counter aa (taa)................................................... 32 7. 16-bit timer/event counter ab (tab)................................................... 34 8. 16-bit timer/event counter t (tmt) ..................................................... 36 9. 16-bit interval timer m (tmm)................................................................. 38 10. motor control function ........................................................................ 39 11. real-time counter ........................................................................................ 41 12. watchdog timer 2 functions ................................................................ 43 13. real-time output function (rto) ......................................................... 44 14. a/d converter ............................................................................................... 45 15. asynchronous serial interface c (uartc) .................................... 47 16. clocked serial interface f (csif) ......................................................... 49 17. i 2 c bus ................................................................................................................ 51 18. can controller............................................................................................. 53 19. usb function controller (usbf) ............................................................ 54 20. ethernet controller ................................................................................. 55 21. dma controller ........................................................................................... 56 22. interrupt/exception processing function..................................... 58 23. key interrupt function (v850es/jf3-e, v850es/jg3-e)...................... 62 24. standby function ........................................................................................ 63 25. reset functions ........................................................................................... 64 26. clock monitor, low-voltage detector ........................................... 65 27. crc functions ............................................................................................... 66 28. regulator function ................................................................................... 67 29. flash memory ................................................................................................ 68 30. on-chip debug function ........................................................................... 69 31. package drawings....................................................................................... 70
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 15 of 75 sep 30, 2010 1. pin functions 1.1 port pins (1/2) pin number pin name i/o function alternate function je3-e jf3-e jg3-e p02 nmi 3 3 3 p03 i/o port 0 2-bit i/o port(v850es/jg3-e) 1-bit i/o port(v850es/je3-e, v850es/jf3-e) input/output can be specified in 1-bit units. intp00/adtrg/exclk ? ? 4 p20 intp01 4 4 5 p21 rtgdiv/rtccl ? ? 6 p22 rtc1hz/intp02 ? ? 7 p23 sif1/txdc1/sda00/intp03 ? 13 16 p24 sof1/rxdc1/sdl00/intp04 ? 14 17 p25 sckf1/tiaa30/toaa30 ? 15 18 p26 i/o port 2 7-bit i/o port(v850es/jg3-e) 5-bit i/o port(v850es/jf3-e) 1-bit i/o port(v850es/je3-e) input/output can be specified in 1-bit units. tiaa31/toaa31/intp05 ? 16 19 p30 txdc0/sif2/tiaa00/toaa00 13 17 20 p31 rxdc0/sof2/tiaa01/toaa01 14 18 21 p32 asckc0/sckf2/tiaa10/toaa10 15 19 22 p33 sif4/tiaa11/toaa11 ? ? 23 p34 sof4/tiaa20/toaa20 ? ? 24 sckf4/tiaa21/toaa21 /toaa1off/intp06 ? ? 80 p35 tiaa21/toaa21/toaa1off/intp06 ? 65 ? p36 txdc2/sda02/ctxd0 note 50 66 81 p37 i/o port 3 8-bit i/o port(v850es/jg3-e) 6-bit i/o port(v850es/jf3-e) 5-bit i/o port(v850es/je3-e) input/output can be specified in 1-bit units. rxdc2/scl02/crxd0 note 51 67 82 p40 sif0/txdc3/sda01/rtp00 52 68 85 p41 sof0/rxdc3/scl01/rtp01 53 69 86 p42 sckf0/tiaa40/toaa40/rtp02 54 70 87 p43 rtp03 ? ? 88 p44 rtp04 ? ? 89 p45 i/o port 4 6-bit i/o port(v850es/jg3-e) 3-bit i/o port(v850es/je3-e, v850es/jf3-e) input/output can be specified in 1-bit units. tiaa41/toaa41/rtp05 ? ? 90 p50 intp07/ddi 16 20 25 p51 intp08/ddo 17 21 26 p52 intp09/dck 18 22 27 p53 intp10/dms 19 23 28 p54 i/o port 5 5-bit i/o port input/output can be specified in 1-bit units. intp11/drst 20 24 29 note available only in on-chip can controller products remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 16 of 75 sep 30, 2010 (2/2) pin number pin name i/o function alternate function je3-e jf3-e jg3-e p70 ani0 64 80 100 p71 ani1 63 79 99 p72 ani2 62 78 98 p73 ani3 61 77 97 p74 ani4 60 76 96 p75 ani5 59 75 95 p76 ani6 58 74 94 p77 ani7 57 73 93 p78 ani8 56 72 92 p79 i/o port 7 10-bit i/o port input/output can be specified in 1-bit units. ani9 55 71 91 p90 toab1t1/toab11/tiab11/kr0/intp12 ? 57 72 p91 toab1b1/tiab10/kr1/toab10 ? 58 73 p92 toab1t2/toab12/tiab12/kr2/intp13 ? 59 74 p93 toab1b2/trgab1/kr3/intp14 ? 60 75 p94 toab1t3/toab13/tiab13/kr4/intp15 ? 61 76 p95 toab1b3/evtb1/kr5/intp16 ? 62 77 p96 tecr0/tit00/kr6/tot00 ? 31 40 p97 tenc00/tit01/kr7/tot01 ? 32 41 p98 tenc01/intp17 ? 33 42 p912 toab1off/intp18 ? 63 78 sif31/intp19 ? ? 30 p913 intp19 ? 25 ? p914 sof3/intp20 ? ? 31 p915 i/o port 9 13-bit i/o port(v850es/jg3-e) 11-bit i/o port(v850es/jf3-e) input/output can be specified in 1-bit units. sckf3 ? ? 32 pdl0 ? ? ? 58 pdl1 ? ? ? 59 pdl2 ? ? ? 60 pdl3 ? ? ? 66 pdl4 ? ? ? 67 pdl5 flmd1 49 64 79 pdl6 ? ? ? 83 pdl7 ? ? ? 84 pdl8 ? ? ? 33 pdl9 ? ? ? 34 pdl10 i/o port dl 11-bit i/o port(v850es/jg3-e) 1-bit i/o port(v850es/jf3-e, v850es/je3-e) input/output can be specified in 1-bit units. ? ? ? 43 remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 17 of 75 sep 30, 2010 1.2 non-port pins (1/5) pin number pin name i/o function alternate function je3-e jf3-e jg3-e adtrg input external trigger input for a/d converter p03/intp00/exclk ? ? 4 ani0 p70 64 80 100 ani1 p71 63 79 99 ani2 p72 62 78 98 ani3 p73 61 77 97 ani4 p74 60 76 96 ani5 p75 59 75 95 ani6 p76 58 74 94 ani7 p77 57 73 93 ani8 p78 56 72 92 ani9 input analog voltage input for a/d converter p79 55 71 91 asckc0 input uartc0 baud rate clock input p32/sckf2/tiaa10/toaa10 15 19 22 av ref0 ? reference voltage input for a/d converter, and p ositive power supply for port 7 ? 1 1 1 av ss ? ground voltage for a/d converter ? 2 2 2 crxd0 note input can receive data input p37/rxdc2/scl02 51 67 82 ctxd0 note output can transmit data output p36/txdc2/sda02 50 66 81 dck input clock input for on-c hip debugging p52/intp09 18 22 27 ddi input data input for on-chip debugging p50/intp07 16 20 25 ddo output data output for on-chip debugging in the on-chip debug mode, high-level output is forcibly set. p51/intp08 17 21 26 dms input mode select signal input for on-chip debugging p53/intp10 19 23 28 drst input reset signal input for on-chip debugging p54/intp11 20 24 29 ev dd ? positive power supply for external (same potential as v dd ) ? 24, 44 29, 52 38, 65 evtab1 input external event count input of tab1 p95/toab1b3/kr5/intp16 ? 62 77 exclk input usb clock signal input p03/intp00/adtrg ? ? 4 flmd0 input ? 42 50 63 flmd1 input flash programming mode setting pins pdl5/ad5 49 64 79 intp00 p03/adtrg/exclk ? ? 4 intp01 p20 4 4 5 intp02 p22/rtc1hz ? ? 7 intp03 p23/sif1/txdc1/sda00 ? 13 16 intp04 p24/sof1/rxdc1/sdl00 ? 14 17 intp05 p26/tiaa31/toaa31 ? 16 19 p35/sckf4/tiaa21/toaa21 /toaa1off ? ? 80 intp06 p35/tiaa21/toaa21/toaa1off ? 65 ? intp07 p50/ddi 16 20 25 intp08 p51/ddo 17 21 26 intp09 p52/dck 18 22 27 intp10 input external interrupt request input (maskable, analog noise elimination). analog noise elimination or digital noise elimination selectable for intp02 pin. p53/dms 19 23 28 note available only in on-chip can controller products remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 18 of 75 sep 30, 2010 (2/5) pin number pin name i/o function alternate function je3-e jf3-e jg3-e intp11 p54/drst 20 24 29 intp12 p90/toab1t1/toab11/tiab11 /kr0 ? 57 72 intp13 p92/toab1t2/toab12/tiab12 /kr2 ? 59 74 intp14 p93/toab1b2/trgab1/kr3 ? 60 75 intp15 p94/toab1t3/toab13/tiab13 /kr4 ? 61 76 intp16 p95/toab1b3/evtab1/kr5 ? 62 77 intp17 p98/tenc01 ? 33 42 intp18 p912/toab1off ? 63 78 p913/sif3 ? ? 30 intp19 p913 ? 25 ? intp20 input external interrupt request input (maskable, analog noise elimination). p914/sof3 ? ? 31 kr0 p90/toab1t1/toab11/tiab11 /intp12 ? 57 72 kr1 p91/toab1b1/tiab10/toab10 ? 58 73 kr2 p92/toab1t2/toab12/tiab12 /intp13 ? 59 74 kr3 p93/toab1b2/trgab1/intp14 ? 60 75 kr4 p94/toab1t3/toab13/tiab13 /intp15 ? 61 76 kr5 p95/toab1b3/evtab1/intp16 ? 62 77 kr6 p96/tecr0/tit00/tot00 ? 31 40 kr7 input key interrupt input (analog noise elimination) p97/tenc00/tit01/tot01 ? 32 41 nmi input external interrupt (non-maskable, ananlog noise elimination) p02 3 3 3 p1col input collision detection input for ethernet ? 46 54 69 p1crs input carrier detection input for ethernet ? 45 53 68 p1mdc output seria transmit clock output ? 32 40 50 p1mdio i/o serial i/o ? 47 55 70 p1rxclk input receive clock input for ethernet ? 48 56 71 p1rxd0 input receive data input for ethernet ? 39 47 57 p1rxd1 input receive data input for ethernet ? 33 41 51 p1rxd2 input receive data input for ethernet ? 34 42 52 p1rxd3 input receive data input for ethernet ? 35 43 53 p1rxdv input receive data valid input for ethernet ? 36 44 54 p1rxer input receive data error input for ethernet ? 37 45 55 p1txclk output transmit clock output for ethernet ? 38 46 56 p1txd0 output transmit data output for ethernet ? 26 34 44 p1txd1 output transmit data output for ethernet ? 27 35 45 p1txd2 output transmit data output for ethernet ? 28 36 46 p1txd3 output transmit data output for ethernet ? 29 37 47 p1txen output transmit data enable output for ethernet ? 31 39 49 p1txer output transmit error output for ethernet ? 30 38 48 remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 19 of 75 sep 30, 2010 (3/5) pin number pin name i/o function alternate function je3-e jf3-e jg3-e regc ? connecting capacitor for regulator output stabilization (4.7 f (preliminary value)) ? 6, 41 6, 49 9, 62 reset input system reset input ? 10 10 13 rtc1hz output real-time counter correction clock (1 hz) output p22/intp02 ? ? 7 rtccl output real-time counter clock (original 32 khz clock) output p21/rtcdiv ? ? 6 rtcdiv output real-time counter clock (divided 32 khz clock) output p21/rtccl ? ? 6 rtp00 p40/sif0/txdc3/sda01 52 68 85 rtp01 p41/sof0/rxdc3/scl01 53 69 86 rtp02 p42/sckf0/tiaa40/toaa40 54 70 87 rtp03 p43 ? ? 88 rtp04 p44 ? ? 89 rtp05 output real-time output port rtp00, rtp01 are n-ch open-drain output selectable. p45tiaa41/toaa41 ? ? 90 rxdc0 p31/sof2/tiaa01/toaa01 14 18 21 rxdc1 p24/sof1/sdl00/intp04 ? 14 17 rxdc2 p37/scl02/crxd0 note 51 67 82 rxdc3 input serial receive data input (uartc0 to uartc3) p41/sof0/scl01/rtp01 53 69 86 sckf0 p42/tiaa40/toaa40/rtp02 54 70 87 sckf1 p25/tiaa30/toaa30 ? 15 18 sckf2 p32/asckc0/tiaa10/toaa10 15 19 22 sckf3 p915 ? ? 32 sckf4 i/o serial clock i/o (csif0 to csif4) p35/tiaa21/toaa21/toaa1off /intp06 ? ? 80 scl00 p24/sof1/rxdc1/intp04 ? 14 17 scl01 p41/sof0/rxdc3/rtp01 53 69 86 scl02 i/o serial clock i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. p37/rxdc2/crxd0 note 51 67 82 sda00 p23/sif1/txdc1/intp03 ? 13 16 sda01 p40/sif0/txdc3/rtp00 52 68 85 sda02 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. p36/txdc2/ctxd0 note 50 66 81 sif0 p40/txdc3/sda01/rtp00 52 68 85 sif1 p23/txdc1/sda00/intp03 ? 13 16 sif2 p30/txdc0/tiaa00/toaa00 13 17 20 sif3 p913/intp19 ? ? 30 sif4 input serial receive data input (csif0 to csif4) p33/tiaa11/toaa11 ? ? 23 sof0 p41/rxdc3/scl01/rtp01 53 69 86 sof1 p24/rxdc1/sdl00/intp04 ? 14 17 sof2 p31/rxdc0/tiaa01/toaa01 14 18 21 sof3 p914/intp20 ? ? 31 sof4 output serial transmit data output (csif0 to csif4) n-ch open-drain output selectable. p34/tiaa20/toaa20 ? ? 24 tecr0 encoder clear input of tmt0 p96/tit00/kr6/tot00 ? 31 40 tenc00 encoder input/external event input/external trigger input of tmt0 p97/tit01/kr7/tot01 ? 32 41 tenc01 input encoder input of tmt0 p98/intp17 ? 33 42 note available only in on-chip can controller products remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 20 of 75 sep 30, 2010 (4/5) pin number pin name i/o function alternate function je3-e jf3-e jg3-e tiaa00 capture trigger input/external event input/external trigger input (taa0) p30/txdc0/sif2/toaa00 13 17 20 tiaa01 capture trigger input (taa0) p31/rxdc0/sof2/toaa01 14 18 21 tiaa10 capture trigger input/external event input/external trigger input (taa1) p32/asckc0/sckf2/toaa10 15 19 22 tiaa11 capture trigger input (taa1) p33/sif4/txdb0/toaa11 ? ? 23 tiaa20 capture trigger input/external event input/external trigger input (taa2) p34/sof4/rxdb0/toaa20 ? ? 24 p35/sckf4/toaa21/toaa1off /intp06 ? ? 80 tiaa21 capture trigger input (taa2) tiaa21/toaa21/toaa1off/int p06 ? 65 ? tiaa30 capture trigger input/external event input/external trigger input (taa3) p25/sckf1/toaa30 ? 15 18 tiaa31 capture trigger input (taa3) p26/toaa31/intp05 ? 16 19 tiaa40 capture trigger input/external event input/external trigger input (taa4) p42/sckf0/toaa40/rtp02 54 70 87 tiaa41 input capture trigger input (taa4) p45/scke0/toaa41/rtp05 ? ? 90 tiab10 capture trigger input/external event input/external trigger input (tab1) n-ch open-drain output selectable. p91/toab1b1/kr1/toab10 ? 58 73 tiab11 p90/toab1t1/toab11/kr0/intp12 ? 57 72 tiab12 p92/toab1t2/toab12/kr2/intp13 ? 59 74 tiab13 input capture trigger input (tab1) n-ch open-drain output selectable. p94/toab1t3/toab13/kr4/intp15 ? 61 76 tit00 p96/tecr0/kr6/tot00 ? 31 40 tit01 input capture trigger input of tmt0 n-ch open-drain output selectable. p97/tenc00/kr7/tot01 ? 32 41 toaa00 p30/txdc0/sif2/tiaa00 13 17 20 toaa01 timer output (taa0) n-ch open-drain output selectable. p31/rxdc0/sof2/tiaa01 14 18 21 toaa10 p32/asckc0/sckf2/tiaa10 15 19 22 toaa11 output timer output (taa1) n-ch open-drain output selectable. p33/sif4/tiaa11 ? ? 23 p35/sckf4/tiaa21/toaa21/intp06 ? ? 80 toaa1off input taa1 high-impedance output control signal input p35/tiaa21/toaa21/intp06 ? 65 ? toaa20 p34/sof4/tiaa20 ? ? 24 p35/sckf4/tiaa21/toaa1off /intp06 ? ? 80 toaa21 timer output (taa2) n-ch open-drain output selectable. p35/tiaa21/toaa1off/intp06 ? 65 ? toaa30 p25/sckf1/tiaa30/ ? 15 18 toaa31 timer output (taa3) n-ch open-drain output selectable. p26/tiaa31/intp05 ? 16 19 toaa40 p42/sckf0/tiaa40/rtp02 54 70 87 toaa41 output timer output (taa4) n-ch open-drain output selectable. p45/scke0/tiaa41/rtp05 ? ? 90 toab10 p91/toab1b1/tiab10/kr1 ? 58 73 toab11 p90/toab1t1/tiab11/kr0/intp12 ? 57 72 toab12 p92/toab1t2/tiab12/kr2/intp13 ? 59 74 toab13 output timer output (tab1) n-ch open-drain output selectable. p94/toab1t3/tiab13/kr4/intp15 ? 61 76 remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 21 of 75 sep 30, 2010 (5/5) pin number pin name i/o function alternate function je3-e jf3-e jg3-e toab1b1 p91/tiab10/kr1/toab10 ? 58 73 toab1b2 p93/trgab1/kr3/intp14 ? 60 75 toab1b3 output pulse signal output for 6-phase pwm low arm of tab1 p95/evtab1/kr5/intp16 ? 62 77 toab1off input tab1 high-impedance output control signal input p912/intp18 ? 63 78 toab1t1 p90/toab11/tiab11/kr0/intp12 ? 57 72 toab1t2 p92/toab12/tiab12/kr2/intp13 ? 59 74 toab1t3 output pulse signal output for 6-phase pwm high arm of tab1. n-ch open-drain output selectable. p94/toab13/tiab13/kr4/intp15 ? 61 76 tot00 p96/tecr0/tit00/kr6 ? 31 40 tot01 output timer output of tmt0 n-ch open-drain output selectable p97/tenc00/tit01/kr7 ? 32 41 trgab1 input external trigger input of tab1 n-ch open-drain output selectable p93/toab1b2/kr3/intp14 ? 60 75 txdc0 p30/sif2/tiaa00/toaa00 13 17 20 txdc1 p23/sif1/sda00/intp03 ? 13 16 txdc2 p36/sda02/ctxd0 note 50 66 81 txdc3 output serial transmit data output (uartc0 to uartc3) n-ch open-drain output selectable. p40/sif0/sda01/rtp00 52 68 85 udmf usb data i/o ( ? ) function ? 21 26 35 udpf i/o usb data i/o (+) function ? 22 27 36 uv dd ? 3.3 v positive power supply for usb ? 23 28 37 v dd ? positive power supply for internal circuit ? 5 5 8 v ss ? ground potential for internal circuit ? 7 7 10 x1 input ? 8 8 11 x2 ? connecting resonator for main clock ? 9 9 12 xt1 input ? 8 11 14 xt2 ? connecting resonator for subclock ? 9 12 15 note available only in on-chip can controller products. remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 22 of 75 sep 30, 2010 1.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connecti on of unused pins are shown in table 1-1. for the schematic circuit diagram of each type, refer to figure 1-1 . table 1-1. types of pin i/o circuits (1/3) pin name alternate function i/o circuit type recommended connection of unused pins je3-e jf3-e jg3-e p02 nmi 3 3 3 p03 intp00/adtrg/exclk 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. ? ? 4 p20 toab02/intp01 4 4 5 p21 rtcdiv/rtccl ? ? 6 p22 rtc1hz/intp02 ? ? 7 p23 sif1/txdc1/sda00/intp03 ? 13 16 p24 sof1/rxdc1/scl00/intp04 ? 14 17 p25 sckf1/tiaa30/toaa30 ? 15 18 p26 tiaa31/toaa31/intp05 ? 16 19 p27 tiab03/toab03/intp21 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. 4 4 5 p30 txdc0/sif2/tiaa00/toaa00 13 17 20 p31 rxdc0/sof2/tiaa01/toaa01 14 18 21 p32 asckc0/sckf2/tiaa10/toaa10 15 19 22 p33 sif4/tiaa11/toaa11 ? ? 23 p34 sof4/tiaa20/toaa20 ? ? 24 sckf4/tiaa21/toaa21 /toaa1off/intp06 ? ? 80 p35 tiaa21/toaa21/toaa1off/intp06 ? 65 ? p36 txdc2/sda02/ctxd0 note 50 66 81 p37 rxdc2/scl02/crxd0 note 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. 51 67 82 p40 sif0/txdc3/sda01/rtp00 52 68 85 p41 sof0/rxdc3/scl01/rtp01 53 69 86 p42 sckf0/tiaa40/toaa40/rtp02 54 70 87 p43 rtp03 ? ? 88 p44 rtp04 ? ? 89 p45 tiaa41/toaa41/rtp05 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. ? ? 90 p50 intp07/ddi 16 20 25 p51 intp08/ddo 17 21 26 p52 intp09/dck 18 22 27 p53 intp10/dms 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. 19 23 28 p54 intp11/drst 10-n input: independently connect to v ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. 20 24 29 p70 to p79 ani0 to ani9 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. 64 to 55 80 to 71 100 to 91 note available only in on-chip can controller products. remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 23 of 75 sep 30, 2010 table 1-1. types of pin i/o circuits (2/3) pin name alternate function i/o circuit type recommended connection of unused pins je3-e jf3-e jg3-e p90 toab1t1/toab11/tiab11/kr0 /intp12 ? 57 72 p91 toab1b1/tiab10/kr1/toab10 ? 58 73 p92 toab1t2/toab12/tiab12/kr2 /intp13 ? 59 74 p93 toab1b2/trgab1/kr3/intp14 ? 60 75 p94 toab1t3/toab13/tiab13/kr4 /intp15 ? 61 76 p95 toab1b3/evtb1/kr5/intp16 ? 62 77 p96 tecr0/tit00/kr6/tot00 ? 31 40 p97 tenc00/tit01/kr7/tot01 ? 32 41 p98 tenc01/intp17 ? 33 42 p912 toab1off/intp18 ? 63 78 sif3/intp19 ? ? 30 p913 intp19 ? 25 ? p914 sof3/intp20 ? ? 31 p915 sckf3 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. ? ? 32 pdl0 to pdl4 ? 5 ? ? 58 to 67 pdl5 flmd1 5 49 64 79 pdl6 to pdl10 ? 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. ? ? 83,84, 33,34, 43 av ref0 ? ? directly connect to v dd and always supply power. 1 1 1 av ss ? ? directly connect to v ss . 2 2 2 ev dd ? ? directly connect to v dd and always supply power. 24, 44 29, 52 38, 65 flmd0 ? ? connect to v ss in other than flash mode. 42 50 63 p1col ? 5 46 54 69 p1crs ? 5 45 53 68 p1mdio ? 5 47 55 70 p1rxclk ? 5 48 56 71 p1rxd0 ? 5 39 47 57 p1rxd1 ? 5 33 41 51 p1rxd2 ? 5 34 42 52 p1rxd3 ? 5 35 43 53 p1rxdv ? 5 36 44 54 p1rxer ? 5 37 45 55 p1txclk ? 5 independently connect to ev dd or v ss via a resistor. 38 46 56 p1mdc ? 5 32 40 50 p1txd0 ? 5 26 34 44 p1txd1 ? 5 27 35 45 p1txd2 ? 5 28 36 46 p1txd3 ? 5 29 37 47 p1txen ? 5 31 39 49 p1txer ? 5 leave open. 30 38 48 remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 24 of 75 sep 30, 2010 table 1-1. types of pin i/o circuits (3/3) pin name alternate function i/o circuit type recommended connection of unused pins je3-e jf3-e jg3-e regc ? ? connect to regulator output stabilization (4.7 f (preliminary value)) capacitor. 6, 41 6, 49 9, 62 reset ? 2 ? 10 10 13 udmf ? ? leave open. 21 26 35 udpf ? ? leave open. 22 27 36 uv dd ? ? directly connect to v dd and always supply power. 23 28 37 v dd ? ? ? 5 5 8 v ss ? ? ? 7 7 10 x1 ? ? ? 8 8 11 x2 ? ? ? 9 9 12 xt1 ? 16-c connect to v ss via a resistor. 8 11 14 xt2 ? 16-c leave open. 9 12 15 remark je3-e: v850es/je3-e, jf3-e: v 850es/jf3-e, jg3-e: v850es/jg3-e
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 1. pin functions r01ds0029ej0001 rev.0.01 page 25 of 75 sep 30, 2010 figure 1-1. pin i/o circuits type 2 type 5 type 10-d type 10-n type 11-g type 16-c schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out ev dd v ss n-ch input enable data output disable ev dd v ss note note p-ch in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch v ref0 (threshold voltage) comparator input enable + _ av ss av ss data output disable ev dd v ss p-ch in/out n-ch open drain input enable ocdm0 bit n-ch p-ch feedback cut-off xt1 xt2 note hysteresis characteristics are not available in port mode.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 2. cpu functions r01ds0029ej0001 rev.0.01 page 26 of 75 sep 30, 2010 2. cpu functions the cpu of the v850es/je3-e, v850 es/jf3-e and v850es/jg3-e is based on risc architecture and executes most instructions in a 1-clock cycle by using a 5-stage pipeline. the features of the cpu are as follows. { minimum instruction execution time: 20 ns (@ 50 mhz operation with main clock (f xx )) 30.5 s (@ 32.768 khz operation with sub-clock (f xt )) { memory space program space: 64 mb linear data space: 4 gb linear { general-purpose registers: 32 bits 32 registers { internal 32-bit architecture { 5-stage pipeline control { multiplication/division instructions { saturation operation instructions { 1-clock 32-bit shift instruction { load/store instructions with long/short format { internal memory table 2-1. rom/ram ram size generic name products flash memory size internal ram data ram pd70f3826 64 kb 16 kb 16 kb pd70f3827 128 kb 32 kb 16 kb pd70f3828 256 kb 48 kb 16 kb v850es/je3-e pd70f3829 256 kb 48 kb 16 kb pd70f3830 64 kb 16 kb 16 kb pd70f3831 128 kb 32 kb 16 kb pd70f3832 256 kb 48 kb 16 kb v850es/jf3-e pd70f3833 256 kb 48 kb 16 kb pd70f3834 64 kb 16 kb 16 kb pd70f3835 128 kb 32 kb 16 kb pd70f3836 256 kb 48 kb 16 kb v850es/jg3-e pd70f3837 256 kb 48 kb 16 kb { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 3. memory map r01ds0029ej0001 rev.0.01 page 27 of 75 sep 30, 2010 3. memory map the memory maps of the v850es/je3-e, v850 es/jf3-e and v850es/jf3- e are shown below. { address space program space internal ram area use prohibited area use prohibited area internal rom area data space image 63 image 1 image 0 peripheral i/o area internal ram area use prohibited area internal rom area 16 mb 64 mb 4 gb 64 mb ? ? ? use prohibited area
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 3. memory map r01ds0029ej0001 rev.0.01 page 28 of 75 sep 30, 2010 { data memory map (80 kb) use prohibited use prohibited internal rom area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) usb function/ ethernet/data ram area (2 mb) use prohibited note 1 programmable peripheral i/o area note 2 or use prohibited note 3 00000000h 001fffffh 00200000h 003fffffh 00400000h 03ffffffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03fef000h 03feefffh 03feffffh 00000000h 00100000h 001fffffh 000fffffh 03fec000h 03febfffh 03fec000h notes 1. use of addresses 03fef000h to 03feffffh is prohibited becau se they overlap an on-chip peripheral i/o area. 2. the programmable peripheral i/o area is seen as 256 mb areas in the 4 gb address space. 3. in on-chip can controller products, addre sses 03fec000h to 03fee fffh are assigned to addresses 03fec000h to 03fecbffh as a programma ble peripheral i/o area. in other products, use of this area is prohibited.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 4 . .ports r01ds0029ej0001 rev.0.01 page 29 of 75 sep 30, 2010 4. ports the number of i/o ports of the v850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of ports (5 v tolerant) 26 (12) 42 (28) 62 (35) the following figure shows the bas ic configurations of ports. (a) v850es/je3-e p50 p54 port 5 p70 p79 port 7 pdl5 port dl p30 p32 port 3 p20 port 2 port 0 p36 p37 p40 p42 port 4 p02 (b) v850es/jf3-e p50 p54 port 5 p70 p79 port 7 pdl5 port dl p30 p32 port 3 p20 p23 p26 port 2 port 0 p35 p37 p40 p45 port 4 p02 p912 p913 p90 p98 port 9 (c) v850es/jg3-e p50 p54 port 5 p70 p79 port 7 pdl0 pdl10 port dl p30 p37 port 3 p20 p26 port 2 port 0 p40 p45 port 4 p02 p03 p912 p915 p90 p98 port dh
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 5. clock generation function r01ds0029ej0001 rev.0.01 page 30 of 75 sep 30, 2010 5. clock generation function the clock generation function has the following features. { main clock oscillator ? pll mode ( 8): f x = 3 to 6.25 mhz (f xx = 24 to 50 mhz) ? clock through mode: f x = 3 to 6.25 mhz (f xx = 3 to 6.25 mhz) { subclock oscillator ? f xt = 32.768 khz { internal oscillator (f r = 220 khz) ? default clock of watchdog timer ? sampling clock for clock monitor f unction of the main clock oscillator ? can be used as the internal system cl ock after the main clock is stopped { internal system clock generation ? 7 levels (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 5. clock generation function r01ds0029ej0001 rev.0.01 page 31 of 75 sep 30, 2010 the following figure shows the configurat ion of the clock generation function. frc bit mfrc bit ck2-ck0 bit selpll bit pllon bit ck3 bit stop mode subclock oscillator prescaler 1 prescaler 2 idle control halt control halt mode cpu clock rtc clock rtc clock, wdt clock peripheral clock (include ethernet) usb clock wdt clock, timer m clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 exclk note x1 x2 idle mode ucksel bit pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xt f xt f xx f x f r idle control selector selector selector selector selector note v850es/jg3-e only remark f x : main clock oscillation frequency f r : internal oscillation frequency f xx : main clock frequency f xt : subclock frequency f cpu : cpu clock frequency f clk : internal system clock frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 6. taa r01ds0029ej0001 rev.0.01 page 32 of 75 sep 30, 2010 6. 16-bit timer/event counter aa (taa) the number of taa of the v 850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 5 channels (taa0 to taa4 note ) 5 channels (taa0 to taa4) 5 channels (taa0 to taa4) number of timer output 4 7 10 note taa2 and taa3 have interval timer function only. the timer/counter function has the following features. ? 16 bit timer/counter (taan) ? clock selection: 8 ways ? capture/trigger input pins (tiaa n0, tiaan1): 2 ? external event count input pin note : 1 ? external trigger input pin note : 1 ? timer/counter: 1 ? capture/compare registers: 2 (32-bit capture function available by using a cascade connection with timer aa.) ? capture/compare match interrupt request signals: 2 ? timer output pins (toaan0, toaan1): 2 the taan function has t he following features. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? timer tuning function ? simultaneous start function note the external event count input pin and external trigger input pin also function as the capture trigger input pin (tiaan0). remark n = 0 to 4
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 6. taa r01ds0029ej0001 rev.0.01 page 33 of 75 sep 30, 2010 the following figure shows the configuration of taa. internal bus internal bus taancnt 16-bit counter taanccr0 ccr0 buffer register taanccr1 ccr1 buffer register clear inttaanov toaan0 toaan1 inttaancc0 inttaancc1 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiaan0 tiaan1 selector selector output controller edge detector note note f xx /2, f xx /4, f xx /8, f xx /16, f xx /64, f xx /256, f xx /512, f xx /1024 for taa2, taa3 remark f xx = main clock frequency n = 0 to 4
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 7. tab r01ds0029ej0001 rev.0.01 page 34 of 75 sep 30, 2010 7. 16-bit timer/event counter ab (tab) the number of tab of the v 850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 1 channel (tab1 note ) 1 channel (tab1) 1 channel (tab1) number of timer output - 4 4 note interval timer function only. the tab function has the following features. ? 16-bit timer/counter (tab1) ? clock selection: 8 ways ? capture/trigger input pins (tiab10 to tiab13): 4 ? external event count input pin (evtab1): 1 ? external trigger input pin (trgab1): 1 ? timer/counter: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? timer output pins (toab10 to toab13 ): 4 the tab1 function has the following features . ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? triangular wave pwm output ? timer tuning function
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 7. tab r01ds0029ej0001 rev.0.01 page 35 of 75 sep 30, 2010 the following figure shows th e configuration of tab. tab1cnt tab1ccr0 ccr0 buffer register tab1ccr1 ccr1 buffer register tab1ccr2 toab10 inttab1ov ccr2 buffer register tab1ccr3 ccr3 buffer register toab11 toab12 toab13 inttab1cc0 inttab1cc1 inttab1cc2 inttab1cc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiab10 trgab1 evtab1 tiab11 tiab12 tiab13 internal bus internal bus 16-bit counter clear selector selector output controller edge detector remark f xx : main clock frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 8. tmt r01ds0029ej0001 rev.0.01 page 36 of 75 sep 30, 2010 8. 16-bit timer/event counter t (tmt) the number of tab of the v 850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 1 channel (tmt0 note ) 1 channel (tmt0) 1 channel (tmt0) number of timer output - 2 2 note interval timer function only. the tmt function has the following features. ? 16 bit timer/counter (tmt) ? clock selection: 8 ways ? capture/trigger input pins (tit00, tit01) : 2 ? external event count input pin note 1 : 1 ? encoder input pin (tenc00, tenc01) : 2 ? encoder clear input pin (tecr0) : 1 ? external trigger input pin note 1 : 1 ? timer/counter: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins (tot00, tot01) : 2 the tmt function has the following features note 2 . ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? triangular wave pwm output ? encoder count function notes 1. the external trigger input pin and the external event co unt input pin also function as the encoder input pin (tenc00) 2. the tmt0 function of v850es/ je3-e is only interval timer.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 8. tmt r01ds0029ej0001 rev.0.01 page 37 of 75 sep 30, 2010 the following figure shows the configuration of tmt. f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 internal bus internal bus tt0cnt tt0tcw tt0ccr0 ccr1 buffer register tt0ccr1 16-bit counter ccr0 buffer register counter control clear inttt0ov inttt0cc0 tot00 tot01 inttt0cc1 inttt0ec tit01 tit00 tecr0 tenc00 tenc01 sampling clock f xx f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator selector selector output controller remark f xx : main clock frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 9. tmm r01ds0029ej0001 rev.0.01 page 38 of 75 sep 30, 2010 9. 16-bit interval timer m (tmm) the number of tmm of the v 850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 4 channels (tmm0 to tmm3) 4 channels (tmm0 to tmm3) 4 channels (tmm0 to tmm3) the tmm function has t he following features. ? interval function ? clock selection: 8 ways ? 16 bit counter 1 (not available to counter lead in timer count operation) ? compare register 1 (not available to write compare register in timer count operation) ? compare match interrupt 1 the following figure shows th e configuration of tmm. tmnctl0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /512 f xx /1024 controller clear inttmneq0 tmncmp0 tmnce tmncks2 tmncks1tmncks0 internal bus 16-bit counter selector match note note in case of tmm0, f xx , f xx /2, f xx /4, f xx /64, f xx /512, f xx /1048, f r , f xt . remark f xx : main clock frequency f xt : subclock frequency f r : internal oscillation frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 10. motor control function r01ds0029ej0001 rev.0.01 page 39 of 75 sep 30, 2010 10. motor control function in the v850es/jf3-e and v850es/jg 3-e, one channel of motor control function is provided. timer ab1 (tab) and the tab option (tabop) can be used as an inverter function that controls a motor. it performs a tuning operation with timer aa4 (taa4) and a/d conversion of the a/d conv erter can be started when the value of tab matches the value of taa4. the following operations can be performed as motor control functions. ? 6-phase pwm output function with 16-bit resoluti on (with dead-timer, for upper and lower arms) ? timer tuning operation function (tunable with taa4) ? cycle setting function (cycle can be changed during operation of cres t or valley interrupt) ? compare register rewriting: anytime rewrit e, batch rewrite, or intermittent rewrite (selectable during tab operation) ? interrupt and transfer culling functions ? dead-time setting function ? a/d trigger timing function of the a/d conv erter (four types of timing can be generated) ? 0% output and 100% output available ? 0% output and 100% output selectable by crest interrupt and valley interrupt ? forced output stop function ? at valid edge detection by external pi n input (intp06/toaa1 off, intp18/toab1off) ? when stoppage of the main clock oscillat ion is detected by clock monitor function
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 10. motor control function r01ds0029ej0001 rev.0.01 page 40 of 75 sep 30, 2010 the following figure shows the configur ation of motor control function. carrier 3-phase pwm generation tab1 6-phase pwm generation with dead time from 3-phase pwm culling control a/d trigger selection tab option a/d trigger timing generation in tuning operation with tab1 taa4 ? pwm generation taa1 ? interrupt control intc high-impedance output controller toab1t1 toab1b1 toab1t2 toab1b2 toab1t3 toab1b3 toaa11 toab10 intp18/toab1off valley interrupt (inttab1ov) crest interrupt (inttab1cc0) edge detection edge detection noise elimination intp06/toaa1off noise elimination a/d trigger of a/d converter ? ? ? ? ? ?
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 11. real-time counter r01ds0029ej0001 rev.0.01 page 41 of 75 sep 30, 2010 11. real-time counter in the v850es/jx3-e, one channel of real-time counter is provided. the real-time counter ha s the following features. ? it has counters for year, month, week, day, hours, minutes and seconds, and it can count up to 99 years. ? the year, month, week, day, hour, minute and second counters show the count in bcd code note 1 . ? alarm interrupt function ? fixed-cycle interrupt function (cycle: 1 month to 0.5 seconds) ? interval interrupt functi on (cycle: 1.95 to 125 ms) ? 1 hz pin output ? 32.768 khz pin output ? 512 hz or 16.384 khz pin output ? watch error correction function ? subclock operation or main clock operation note 2 selectable notes 1. bcd (binary-coded decimal) code is the code that represents each digit of a decimal number in 4-bit binary numerals. 2. the main clock can be divided into 32.768 khz f brg with the baud rate generato r dedicated to the real-time counter.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 11. real-time counter r01ds0029ej0001 rev.0.01 page 42 of 75 sep 30, 2010 the following figure shows the conf iguration of real-time timer. count enable/ disable circuit sub-counter (16-bit) second counter (7-bit) second counter write buffer minute counter write buffer hour counter write buffer day counter write buffer week counter write buffer minute counter (7-bit) hour counter (6-bit) day counter (3-bit) day-of week counter (3-bit) intrtc0 intrtc1 1 minute 1 hour 1 day 1 month count clock = 32.768 khz f xt f xt /2 6 f xt /2 f xt /2 6 f xt /2 7 f xt /2 8 f xt /2 9 f xt /2 10 f xt /2 11 f xt /2 12 f brg month counter write buffer year counter write buffer month counter (5-bit) year counter (8-bit) minute alarm ict2 to ict0 hour alarm day-of-week alarm 12-bit counter ckdiv rinte intrtc2 rtcdiv cloe2 rtccl cloe0 rtc1hz cloe1 selector selector selector selector remark f brg : real-time counter count clock frequency f xt : subclock frequency intrtc0: real-time counter fixed-cycle signal intrtc1: real-time counter alarm match signal intrtc2: real-time counter interval signal
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 12. wdt2 r01ds0029ej0001 rev.0.01 page 43 of 75 sep 30, 2010 12. watchdog timer 2 functions in the v850es/jx3-e, one channel of watchdog timer 2 is provided. the watchdog timer has the following functions. ? reset mode: reset operation upon overflow of watchdog timer (generates the wdt2res signal) ? non-maskable interrupt request mode: nmi operati on upon overflow of watchdog timer (generates the intwdt2 signal) the following figure shows the configurati on of the watchdog timer functions. f x /2 7 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f r /2 3 wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f x /2 16 to f x /2 23 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear remark f x : main clock oscillation frequency f r : internal oscillation clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdt2res: watchdog timer 2 reset signal
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 13. rto r01ds0029ej0001 rev.0.01 page 44 of 75 sep 30, 2010 13. real-time output function (rto) in the v850es/jx3-e, one channel of real-time output is provided. the rto has the following features. ? 6-bit real-time output port: 1 channel ? the real-time output port can be set to the port mode or real-time output port mode in 1-bit units. the rto has the following configurations. real-time output buffer register 0h (rtbh0) real-time output latch 0h inttaa0cc0 inttaa4cc0 inttaa5cc0 real-time output latch 0l rtpoe0 rtpeg0 byte0 extr0 real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 real-time output port mode register 0 (rtpm0) 4 2 2 4 real-time output buffer register 0l (rtbl0) rtp04, rtp05 rtp00 to rtp03 internal bus selector
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 14. a/d converter r01ds0029ej0001 rev.0.01 page 45 of 75 sep 30, 2010 14. a/d converter an a/d converter unit with ten channel s is provided in the v850es/jx3-e. the a/d converter has t he following features. { 10-bit resolution { 10 channels { successive approximation method { operating voltage: av ref0 = 3.0 to 3.6 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { power-fail monitor function (conversion result compare function)
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 14. a/d converter r01ds0029ej0001 rev.0.01 page 46 of 75 sep 30, 2010 the following figure shows the confi guration of the a/d converter. ani0 : : : : ani1 ani2 ani9 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm ada0cr0 ada0cr1 . . . ada0cr7 ada0cr8 ada0cr9 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit inttaa2cc0 inttaa2cc1 tqtadto note ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac selector selector note timer trigger signal from 6-phase pwm output circuit (tabop)
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 15. uartc r01ds0029ej0001 rev.0.01 page 47 of 75 sep 30, 2010 15. asynchronous serial interface c (uartc) the number of uartc of the v850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 3 channels (uartc0, uartc2 and uartc3) 4 channels (uartc0 to uartc3) 4 channels (uartc0 to uartc3) the uartc has the following features. { transfer rate: 300 bps to 3.125 mbps (using internal system clock of 24 mhz and dedicated baud rate generator) { full-duplex communication: on-chip uartcn receive data register (ucnrx) on-chip uartcn transmit data register (ucntx) { 2-pin configuration: txdcn: transmit data output pin rxdcn: receive data input pin { reception error detect function ? parity error ? framing error ? overrun error ? lin communication data consistency error detect function ? sbf reception success detect function { interrupt sources: 2 types ? reception completion interrupt (intucnr): this interrupt occurs upon transfer of receive data from the receive shift register to receive data regist er after serial tr ansfer completion, in the reception enabled status. ? transmission enable interrupt (intucnt): this interrupt occurs upon transfer of trans mit data from the transmit data register to the transmit shi ft register in the transmission enabled status. { character length: 7, 8, 9 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb-/lsb-first transfer selectable { transmit/receive data inverted input/output possible { sbf (sync break field) transmission/reception in t he lin (local interconnect network) communication format possible ? 13 to 20 bits are selectable for sbf transmission ? recognition of 11 bits or more pos sible for sbf reception in lin format ? sbf reception flag provided
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 15. uartc r01ds0029ej0001 rev.0.01 page 48 of 75 sep 30, 2010 the following figure shows the configuration of uartc. ucnotp0 ucnctl0 ucnstr ucnctl1 ucnctl2 ucnrx ucntx intucnr intucnt txdcn rxdcn f xx to f xx /2 10 asckc0 note internal bus receive shift register filter selector transmission controller reception controller baud rate generator reception unit transmission unit transmit shift register baud rate generator selector internal bus clock selector note uartc0 only remark f xx : main clock frequency remark
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 16. csif r01ds0029ej0001 rev.0.01 page 49 of 75 sep 30, 2010 16. clocked serial interface f (csif) the number of csif of the v850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 2 channels (csif0 and csif2) 3 channels (csif0 to csif2) 5 channels (csif0 to csif4) { transfer rate: 8 mbps max. (f xx = 50 mhz, using internal clock) { master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { interrupt request signals (intcfnt, intcfnr) { serial clock and data phase switchable { transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { 3-wire sofn: serial data output sifn: serial data input sckfn: serial clock i/o transmission mode, reception mode, an d transmission/reception mode specifiable
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 16. csif r01ds0029ej0001 rev.0.01 page 50 of 75 sep 30, 2010 the following figure shows the configuration of csif. internal bus cfnctl2 cfnctl0 cfnstr intcfnr sofn intcfnt cfntx so latch cfnrx cfnctl1 sifn f brg f cclk f xx /4 f xx /6 f xx /8 f xx /12 f xx /16 f xx /32 sckfn controller shift register phase control selector phase control remark f xx : main clock frequency f brg : baud rate generator count clock f cclk : communication clock
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 17. i 2 c bus r01ds0029ej0001 rev.0.01 page 51 of 75 sep 30, 2010 17. i 2 c bus the number of i 2 c bus of the v850es/jx3-e is shown below. product name v850es/jf3-e v850es/jf-e v850es/jg3-e number of channel 2 channels (i 2 c01 and i 2 c02) 3 channels (i 2 c00 to i 2 c02) 3 channels (i 2 c00 to i 2 c02) { transfer rate: standard mode (100 kbps max.)/high-speed mode (400 kbps max.) { conforms to i 2 c bus format (multimaster supported) { 2-wire scl0n: serial clock pin sda0n: serial data bus pin
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 17. i 2 c bus r01ds0029ej0001 rev.0.01 page 52 of 75 sep 30, 2010 the following figure shows the configuration of i 2 c. iic status register n (iicsn) iic control register n (iiccn) slave address register n (svan) iic shift register n (iicn) iicen dq cln1, cln0 trcn dfcn dfcn sda0n scl0n intiicn iic shift register n (iicn) iiccn.sttn, sptn iicsn.mstsn, excn, coin iicsn.mstsn, excn, coin lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn cldn dadn smcn dfcn cln1 cln0 clxn iic clock select register n (iiccln) stcfn iicbsyn stcenn iicrsvn iic flag register n (iicfn) iic function expansion register n (iicxn) fxx iic division clock select register n (ocksn) fxx to fxx/5 ocksthn ocksenn ocksn1 ocksn0 internal bus noise eliminator noise eliminator bus status detector match signal so latch set clear n-ch open-drain output n-ch open-drain output data retention time correction circuit start condition generator stop condition generator ack generator wakeup controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler start condition detector internal bus prescaler remark f xx : main clock frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 18. can controller r01ds0029ej0001 rev.0.01 page 53 of 75 sep 30, 2010 18. can controller in the pd70f3829, 70f3833, 70f3837, one channel of can controller is provided. ? compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) ? standard frame and extended fram e transmission/reception enabled ? transfer rate: 1 mbps max. (can clock input 8 mhz) ? 32 message buffers/channels ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel the following figure shows the conf iguration of can controller. ctxd0 crxd0 cpu can module can ram internal bus mac (memory access controller) npb interface interrupt request intc0trx intc0rec intc0err intc0wup can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 cnmask1 cnmask2 cnmask3 cnmask4 ... can_h0 can_l0 can bus
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 19. usbf r01ds0029ej0001 rev.0.01 page 54 of 75 sep 30, 2010 19. usb function controller (usbf) in the v850es/jx3-e, one channel of usbf is provided. ? conforms to the universal serial bus (usb) specification. ? usb 2.0-compatible full-speed transfer (12 mbps) supported ? endpoint for transfer incorporated endpoint name fifo size (bytes) transfer type remark endpoint0 read 64 control transfer ? endpoint0 write 64 control transfer ? endpoint1 64 2 bulk 1 transfer (in) 2-buffer configuration endpoint2 64 2 bulk 1 transfer (out) 2-buffer configuration endpoint3 64 2 bulk 2 transfer (in) 2-buffer configuration endpoint4 64 2 bulk 2 transfer (out) 2-buffer configuration endpoint7 8 interrupt transfer (in) ? the following figure shows the configur ation of usb function controller. usbf controller sie i/o buffer endpoint endpoint0 read (64 bytes) endpoint0 write (64 bytes) endpoint1 (64 bytes 2) endpoint2 (64 bytes 2) endpoint3 (64 bytes 2) endpoint4 (64 bytes 2) endpoint7 (8 bytes) usbf interrupt (intusbf0) internal cpu usb resume interrupt (intusbf1) usb clock udmf udpf bridge circuit bridge interrupt enable register (brginte) remark area enclosed with dashed line: function s included in usb function controller
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 20. ethernet controller r01ds0029ej0001 rev.0.01 page 55 of 75 sep 30, 2010 20. ethernet controller in the v850es/jx3-e, one channel of ethernet controller is provided. { 10 mbps/100 mbps mac function conforming to the ieee802.3 standard ? full-duplex and half-duplex communications and a flow control function are supported ? on-chip packet filtering function based on address type ? on-chip vlan detection function { ethernet-dedicated dma controller ? reception status dma transfer possible ? reading (in pointer-chain format), analysis, and writing back of buffer descriptors possible ? interrupt control functions for packet transfers { fifo controller ? transmission/reception fifo size: transmi ssion fifo (2 kb), reception fifo (2 kb) ? on-chip fifo status register ? interrupts occur in accordan ce with the transmission/recep tion status and fifo status. { mii is supported as the interface with physical-layer devices (phy) { on-chip reception checksum calculat ion function conforming to rfc1071 the following figure shows the configur ation of usb function controller. internal bus interface v850es/jx3-e mii/rmii i/o buffer tpo+ tpo- tpi+ tpi- phy dma controller ethernet mac fifo controller transmission fifo (2 kb) internal bus reception fifo (2 kb)
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 21. dma controller r01ds0029ej0001 rev.0.01 page 56 of 75 sep 30, 2010 21. dma controller in the v850es/jx3-e, four channels of dma controller are provided. { 4 independent dma channels { transfer unit: 8/16 bits { maximum transfer count: 65,536 (2 16 ) { transfer type: two-cycle transfer { transfer mode: single transfer mode { transfer requests ? request by interrupts from on-chip peripheral i/o (s erial interface, timer/c ounter, real-time counter, a/d converter) or interrupts from external input pin ? requests by software trigger { transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 21. dma controller r01ds0029ej0001 rev.0.01 page 57 of 75 sep 30, 2010 the following figure shows the conf iguration of dma controller. cpu dmac dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control remark n = 0 to 3
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 22. interrupt/exception processing function r01ds0029ej0001 rev.0.01 page 58 of 75 sep 30, 2010 22. interrupt/exception processing function the features of interrupt/exception pr ocessing function is shown below. { interrupts internal external non maskable maskable total non maskable maskable total v850es/je3-e pd70f3826 1 53 54 1 6 7 pd70f3827 1 53 54 1 6 7 pd70f3828 1 53 54 1 6 7 pd70f3829 1 57 58 1 6 7 v850es/jf3-e pd70f3830 1 56 57 1 18 19 pd70f3831 1 56 57 1 18 19 pd70f3832 1 56 57 1 18 19 pd70f3833 1 60 61 1 18 19 v850es/jg3-e pd70f3834 1 60 61 1 21 22 pd70f3835 1 60 61 1 21 22 pd70f3836 1 60 61 1 21 22 pd70f3837 1 64 65 1 21 22 ? 8 levels of programmable priorities ? masks interrupt requests according to priority ? masks can be specified for each maskable interrupt request. ? noise elimination, edge detection, and valid edge s pecification for external interrupt request signals. { exceptions ? software exceptions: 32 sources ? exception trap: 2 sources (ille gal opcode exception, debug trap) interrupt/exception sources are listed in table 22-1.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 22. interrupt/exception processing function r01ds0029ej0001 rev.0.01 page 59 of 75 sep 30, 2010 table 22-1. interrupt source list (1/3) type classification default priority name trigger generating unit interrupt control register je3e jf3e jg3e reset interrupt ? reset reset pin input/reset inpu t from internal source reset ? ? nmi nmi pin valid edge input pin ? non- maskable interrupt ? intwdt2 wdt2 overflow wdt2 ? ? trap0n (n = 0-fh) trap instruction ? ? software exception exception ? trap1n (n = 0-fh) trap instruction ? ? exception trap exception ? ilgop/dbg0 illegal instruct ion code/dbtrap instruction ? ? 0 intlvi detection of low voltage poclvi lviic 1 intp00 detection of external interrupt pin input edge (intp00) pin pic0 2 intp01 detection of external interrupt pin input edge (intp01) pin pic1 3 intp02 detection of external interrupt pin input edge (intp02) pin pic2 ? ? 4 intp03 detection of external interrupt pin input edge (intp03) pin pic3 ? 5 intp04 detection of external interrupt pin input edge (intp04) pin pic4 ? 6 intp05 detection of external interrupt pin input edge (intp05) pin pic5 ? 7 intp06 detection of external interrupt pin input edge (intp06) pin pic6 ? 8 intp07 detection of external interrupt pin input edge (intp07) pin pic7 9 intp08 detection of external interrupt pin input edge (intp08) pin pic8 10 intp09 detection of external interrupt pin input edge (intp09) pin pic9 11 intp10 detection of external interrupt pin input edge (intp10) pin pic10 12 intp11 detection of external interrupt pin input edge (intp11) pin pic11 13 intp12 detection of external interrupt pin input edge (intp12) pin pic12 ? 14 intp13 detection of external interrupt pin input edge (intp13) pin pic13 ? 15 intp14 detection of external interrupt pin input edge (intp14) pin pic14 ? 16 intp15 detection of external interrupt pin input edge (intp15) pin pic15 ? 17 intp16 detection of external interrupt pin input edge (intp16) pin pic16 ? 18 intp17 detection of external interrupt pin input edge (intp17) pin pic17 ? 19 intp18 detection of external interrupt pin input edge (intp18) pin pic18 ? 20 intp19 detection of external interrupt pin input edge (intp19) pin pic19 ? 21 intp20 detection of external interrupt pin input edge (intp20) pin pic20 ? ? 32 inttab1ov tab1 over flow tab1 tab1ovic 33 inttab1cc0 tab1 capture 0/co mpare 0 match tab1 tab1ccic0 34 inttab1cc1 tab1 capture 1/co mpare 1 match tab1 tab1ccic1 35 inttab1cc2 tab1 capture 2/co mpare 2 match tab1 tab1ccic2 36 inttab1cc3 tab1 capture 3/co mpare 3 match tab1 tab1ccic3 37 inttt0ov tmt0 overflow tmt0 tt0ovic 38 inttt0cc0 tmt0 capture 0/co mpare 0 match tmt0 tt0ccic0 39 inttt0cc1 tmt0 capture 1/co mpare 1 match tmt0 tt0ccic1 maskable interrupt 40 inttt0ec tmt0 encoder input tmt0 tt0ecic ? ?
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 22. interrupt/exception processing function r01ds0029ej0001 rev.0.01 page 60 of 75 sep 30, 2010 table 22-1. interrupt source list (2/3 type classification default priority name trigger generating unit interrupt control register je3e jf3e jg3e 41 inttaa0ov taa0 overflow taa0 taa0ovic 42 inttaa0cc0 taa0 capture 0/compare 0 match taa0 taa0ccic0 43 inttaa0cc1 taa0 capture 1/compare 1 match taa0 taa0ccic1 44 inttaa1ov taa1 overflow taa1 taa1ovic 45 inttaa1cc0 taa1 capture 0/compare 0 match taa1 taa1ccic0 46 inttaa1cc1 taa1 capture 1/compare 1 match taa1 taa1ccic1 47 inttaa2ov taa2 overflow taa2 taa2ovic 48 inttaa2cc0 taa2 capture 0/compare 0 match taa2 taa2ccic0 49 inttaa2cc1 taa2 capture 1/compare 1 match taa2 taa2ccic1 50 inttaa3ov taa3 over flow taa3 taa3ovic 51 inttaa3cc0 taa3 capture 0/compare 0 match taa3 taa3ccic0 52 inttaa3cc1 taa3 capture 1/compare 1 match taa3 taa3ccic1 53 inttaa4ov taa4 overflow taa4 taa4ovic 54 inttaa4cc0 taa4 capture 0/compare 0 match taa4 taa4ccic0 55 inttaa4cc1 taa4 capture 1/compare 1 match taa4 taa4ccic1 59 inttm0eq0 tmm0 compare match tmm0 tm0eqic0 60 inttm1eq0 tmm1 compare match tmm1 tm1eqic0 61 inttm2eq0 tmm2 compare match tmm2 tm2eqic0 62 inttm3eq0 tmm3 compare match tmm3 tm3eqic0 67 intcf0r /intuc3r /intiic1 csif0 transfer completi on/uartc3 reception completion/uartc3 reception error/iic1 transfer completion csif0 /uartc3 /iic1 ce0ric /uc3ric /iicic1 68 intcf0t /intuc3t csif0 continuous transfer write enable/ uartc3 continuous transfer write enable csif0 /uartc3 cf0tic /uc3tic 69 intcf1r /intuc1r /intiic0 csif1 reception completion/ csif1 reception error /uartc1 reception comple tion/uartc1 reception error/iic0 transfer completion csif1 /uartc1 /iic0 cf1ric /uc1ric /iicic0 ? ? 70 intcf1t /intuc1t csif1 continuous transfer write enable/ uartc1 continuous transfer write enable csif1 /uartc1 cf1tic /uc1tic ? ? 71 intcf2r /intuc0r csif2 reception completion/csif2 reception error/ uartc0 reception completion/uartc0 reception error csif2 /uartc0 cf2ric /uc0ric 72 intcf2t /intuc0t csif2 continuous transfer write enable/uartc0 continuous transfer write enable csif2 /uartc0 cf2tic /uc0tic 73 intcf3r csif3 reception completion/c sif3 reception error csif3 cf3ric ? 74 intcf3t csif3 continuous trans fer write enable csif3 cf3tic ? 78 intcf4r csif4 reception completion/c sif4 reception error csif4 cf4ric ? 79 intcf4t csif4 continuous trans fer write enable csif4 cf4tic ? 87 intuc2r /intiic2 uartc2 reception completion/uartc2 reception error/iic2 transfer completion uartc2 /iic2 uc2ric /iicic2 88 intuc2t uartc2 continuous trans fer write enable uartc2 uc2tic maskable interrupt 90 intad a/d converter completion a/d adic
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 22. interrupt/exception processing function r01ds0029ej0001 rev.0.01 page 61 of 75 sep 30, 2010 table 22-1. interrupt/exception source list (3/3) type classification default priority name trigger generating unit interrupt control register je3e jf3e jg3e 91 intdma0 dma0 transfer completion dma dmaic0 92 intdma1 dma1 transfer completion dma dmaic1 93 intdma2 dma2 transfer completion dma dmaic2 94 intdma3 dma3 transfer completion dma dmaic3 95 intkr key return interrupt kr kric 96 intrtc0 rtc fixed-cycle signal rtc rtc0ic 97 intrtc1 rtc alarm match rtc rtc1ic 98 intrtc2 rtc interval signal rtc rtc2ic 99 intusbf0 usbf inte rrupt usbf ufic0 100 intusbf1 usbf resume interrupt usbf ufic1 101 intetmrx packet reception ethernet etmrxic 102 intetmtx packet transmission ethernet etmtxic 103 intetmrq received packet re ad request ethernet etmrqic 104 intetmfs fifo stat us ethernet etmfsic 105 intetmts transmission st atus ethernet etmtsic 106 intetmrs reception st atus ethernet etmrsic 107 intetmov statistic counte r overflow ethernet etmovic 108 intetber error interrupt ethernet etberic 110 intc0err can0 error can0 erric0 note 1 note 2 note 3 111 intc0wup1 can0 wakeup can0 wupic0 note 1 note 2 note 3 112 intc0rec can0 reception can0 recic0 note 1 note 2 note 3 maskable interrupt 113 intc0trx can0 transmission can0 trxic0 note 1 note 2 note 3 notes 1. pd70f3829 only 2. pd70f3833 only 3. pd70f3837 only
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 23. key interrupt function r01ds0029ej0001 rev.0.01 page 62 of 75 sep 30, 2010 23. key interrupt function (v850es/jf3-e, v850es/jg3-e) a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7). the following figure shows the configuration of key interrupt. intkr krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 key return mode register (krm)
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 24. standby function r01ds0029ej0001 rev.0.01 page 63 of 75 sep 30, 2010 24. standby function the power consumption of t he system can be effectively reduced by usi ng the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 24-1. table 24-1. standby modes mode function overview halt mode mode to stop only the operating clock of the cpu idle1 mode mode to stop all the operations of the inte rnal circuit except the oscillator, pll operation note , and flash memory idle2 mode mode to stop all the operations of the internal circuit except the oscillator stop mode mode to stop all the operations of the internal circuit except the subclock oscillator subclock operation mode mode to operate internal system clock by subclock sub-idle mode mode to stop all the operations of th e internal circuit except the oscillator in subcloc k operation mode note pll retains the previous operation status. the following figure shows the status tr ansitions of the standby function. reset subclock operation mode (fx operates, pll operates) subclock operation mode (fx stops, pll stops) sub-idle mode (fx operates, pll operates) sub-idle mode (fx stops, pll stops) stop mode (fx stops, pll stops) idle2 mode (fx operates, pll stops) idle1 mode (fx operates, pll operates) idle1 mode (fx operates, pll stops) halt mode (fx operates, pll stops) halt mode (fx operates, pll operates) normal operation mode oscillation stabilization wait clock through mode (pll operates) clock through mode (pll stops) pll mode (pll operates) internal oscillation clock operation wdt overflow oscillation stabilization wait pll lockup time wait oscillation stabilization wait oscillation stabilization wait remark f x : main clock oscillation frequency
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 25. reset functon r01ds0029ej0001 rev.0.01 page 64 of 75 sep 30, 2010 25. reset functions the following reset functions are available. (1) four types of reset sources ? external reset input via the reset pin ? reset via the watchdog timer 2 (wdt2) overflow (wdt2res) ? system reset by comparing the supply voltage and de tection voltage by using the low-voltage detector (lvi) ? system reset by the clock monitor (clm) upon detection of oscillation stop after a reset is released, the source of the reset can be confirmed with the reset source flag register (resf). (2) emergency operation mode if the wdt2 overflows during the main clock oscillatio n stabilization time inserted after reset, a main clock oscillation anomaly is judged and the cpu starts operating on the internal oscillation clock. the outline of the reset f unctions is shown below. clmrf lvirf wdt2rf reset reset source flag register (resf) internal bus wdt2 reset signal clm reset signal lvi reset signal reset signal reset signal reset signal to lvim register clear set set clear clear set remark lvim: low-voltage detection register
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 26. clm, lvi r01ds0029ej0001 rev.0.01 page 65 of 75 sep 30, 2010 26. clock monitor, low-voltage detector (1) clock monitor the clock monitor samples the main clock by using the internal oscillation clock (f r ) and generates a reset request signal when oscillation of the main clock is stopped. (2) low-voltage detector the low-voltage detector (lvi ) has the following functions. ? compares the supply voltage (v dd ) and detection voltage (v lvi ) and generates an interrupt request signal or internal reset signal when v dd < v lvi . ? an interrupt request signal or internal reset signal can be selected. ? can operate in stop mode. ? operation can be stopped by software.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 27. crc function r01ds0029ej0001 rev.0.01 page 66 of 75 sep 30, 2010 27. crc functions the outline of the crc function is shown below. ? crc operation circuit for detection of data block errors ? generation of 16-bit crc code using a crc-ccitt (x 16 + x 12 + x 5 + 1) generation polynomial for blocks of data of any length in 8-bit units ? crc code is set to the crcd data register each time 1-by te data is transferred to t he crcin register, after the initial value is set to the crcd register. crc data register (crcd) (16 bits) crc input register (crcin) (8 bits) crc code generator internal bus internal bus
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 28. regulator function r01ds0029ej0001 rev.0.01 page 67 of 75 sep 30, 2010 28. regulator function the v850es/jx3-e includes a regulator to reduce power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits except the a/d converter and output buffers). the regulator output voltage is set to 2.5 v (typ.). the outline of the regulator functions is shown below. ev dd i/o buffer bidirectional level shifter ev dd i/o buffer regulator sub-oscillator ev dd regc flmd0 v dd ev dd ev dd regc flash memory main oscillator internal digital circuits 2.5 v (typ.) regulator v dd a/d converter usb av ref0 uv dd
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 29. flash memory r01ds0029ej0001 rev.0.01 page 68 of 75 sep 30, 2010 29. flash memory flash memory versions offer the following advant ages for development environments and mass production applications. { for altering software after the v850es/jx3 -e is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. the flash memory in the v850es/jx3-e has the following features. { 4-byte/1-clock access (when instruction is fetched) { memory size: 64/128/256 kb { rewrite voltage: erase/writ e with a single power supply { rewriting method ? rewriting by communication with dedicated flash pr ogrammer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit fu nction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 30. on-chp debug function r01ds0029ej0001 rev.0.01 page 69 of 75 sep 30, 2010 30. on-chip debug function debugging can be implemented with the v850 es/jx3-e mounted on the target system. the nec electronics on-chip debug emulators minicube and minicube2 are planned to support the v850es/jx3-e. { minicube an on-chip debug function is implemen ted by using the dcu (debug control un it) in the v850es/jx3-e, using the drst, dck, dms, ddi, and ddo pins as the debug interface pins. { minicube2 an on-chip debug function is implement ed by using the user resources (on-chip flash memory, internal ram, etc.) instead of the dcu, and using the si f0, sof0, and sckf0 pins or the si f3, sof3, and sckf3 pins or the rxdc0 and txdc0 pins as the interface pins.
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 31. package drawings r01ds0029ej0001 rev.0.01 page 70 of 75 sep 30, 2010 31. package drawings ? v850es/je3-e s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-gah 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) + 0.07 ? 0.03
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 31. package drawings r01ds0029ej0001 rev.0.01 page 71 of 75 sep 30, 2010 ? v850es/jf3-e s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-gak 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 20 40 1 80 21 41 61 60 80-pin plastic lqfp (fine pitch) (12x12) + 0.07 ? 0.03
pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 31. package drawings r01ds0029ej0001 rev.0.01 page 72 of 75 sep 30, 2010 ? v850es/jg3-e 100-pin plastic lqfp (fine pitch) (14x14) s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 16.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 + + + 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p100gc-50-ueu-1 3 3 5 detail of lead end 0.20 0.07 0.075 0.025 0.03 b 25 50 1 100 26 51 75 76
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history pd70f3826, 70f3827, 70f3828, 70f3829, 70f3830, 70f3831, 70f3832, 70f3833, 70f3834, 70f3835, 70f3836, 70f3837 data sheet description rev. date page summary 0.01 sep 30, 2010 ? first eddition issued all documents should contain the following section break and paragraph as the last item. the footers of this document refer to the paragraph in order to re ference the last page of the document. caution: this product uses superflash ? technology licensed from silic on storage technology, inc. eeprom is a trademark of rene sas electronics corporation. minicube is a registered trademark of renesas electronics corporation in japan and germany or a trademark in the united states of america. superflash is a registered trademark of silicon storag e technology, inc. in several countries, including the united states and japan.
1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan, r.o.c. tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2010 renesas electronics corporation. all rights reserved. colophon 1.0

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